Senior Physical ASIC Design Implementation Engineer

Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, for toplevel chips as well as blocklevel blocks in technologies ranging from N3 to 180nm. This with the full understanding of the complete Cadence Innovus Place&Route flow. Additionally, you will take up the role of technical lead in large projects, leading the rest of the backend team involved and to be the connection with the customer.

What you will do

For more than 25 years, imec has been offering an ASIC prototyping and production service to worldwide companies. Imec helps its customers to design their integrated circuits (chips) and bring them from the prototype to the production stage. Our list of customers includes more than 900 universities and companies worldwide. For the further extension of the physical digital implementation group (Back-End group) in DSRD, we are looking for a highly motivated engineer.
DSRD, as part of imec, has an extensive industrial experience, contacts with leading industrial foundries, and long-standing relationships with all the main EDA tool vendors and IP providers. This unit supports worldwide customers in the layout, prototype, fabrication and test of advanced electronic products.
As ASIC design engineer within DSRD, you will be in direct contact with our customers for future projects and as a technical lead bridge the connection to the rest of the backend team involved. You will have full understanding of the complete Cadence Innovus Place&Route flow:

• Technical lead, including customer interaction
• Set up the flow for the specific library set and foundry node used
• Set up low power design (UPF)
• Floorplanning & power grid design
• Detailed Timing Driven Placement
• STA & possible design optimisation for setup
• Clock Tree Synthesis
• Scan chain re-stitching
• Detailed Timing Driven Route (incl. SI)
• IPO’s (in-place optimization) to get the timing in all corners correct
• Solve setup & hold violations
• Sign-off extraction (SPEF/QUANTUS)
• Sign-off timing (TEMPUS)
• Sign-off Power analysis (VOLTUS)
• Physical verification (DRC, ERC, LVS, ANT)
• Logic equivalent check 

For hierarchical designs you can take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks. You will work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out, You are also the technical voice to the customer to discuss his specifications.

Who you are

• You have a Master Degree in Electronics.
• You have at least 10 years of experience in physical implementation in advanced nodes (12 – 3nm) and hierarchical designs. 
• You have experience in power reduction techniques like gated clocks, voltage domains, memory retention and switch off power domains. 
• You have experience in debugging any tool/flow/design issue.
• You have excellent communication skills (English is a must) and can work within an international team. 
• You like to interact with customers.